Fabrication of semiconductor dies with micro-pins and structures produced therewith

ABSTRACT

A method for forming a semiconductor die, comprising forming a trench in a surface of the die; filing the trench with a sacrificial material; patterning the die to form a series of channels extending substantially perpendicularly to the trench; depositing a conductive material in the channels; removing at least a portion of the sacrificial material; and removing portions of the die under the trench so as to separate a portion of the die on one side of the trench from a portion on another side of the trench. The sacrificial material may be patterned so that the channels extend so as to be partially in a portion of the die and partially a portion of the sacrificial material. A series of structures are formed having dies with micro-pins.

FIELD OF THE INVENTION

The present invention relates to the packaging and assembly ofintegrated circuit. More particularly, it relates to a method andapparatus for connecting integrated circuits to one another and to otherdevices so as to preserve space and so as to create compact electronicpackages.

BACKGROUND OF THE INVENTION

Integrated circuits (ICs) or chips are typically connected to packagesor directly on to a system board by use of wire bonds or solder bumpsthat lie on the surface of the ICs. To achieve a compact and higherperformance electronic system, it is desirable to stack ICs (in bare orpackaged form) on top of each other. Such a stack of ICs may then bepackaged using methods that are conventionally used to package an IC andconnected to the next level of packaging.

ICs are typically stacked by use of wire bonds or conductive thru-viasthat are fabricated within the IC. The art of stacking ICs using wirebonds has been previously published in the literature. Examples areKiyono, S. S., Yamada, T., Yonehara K., “Consideration of Chip CircuitDamage on DCS—FBGA Packages,” 52^(nd) Electronic Components andTechnology Conference, May 2002, San Diego, Calif. and Intel StackedChip Scale Packaging Products, available athttp://www.intel.com/design/flcomp/prodbref/298051.htm. In thisapproach, a smaller chip is attached on top of a larger chip with theuse of an adhesive. The smaller chip is either wire-bonded to a portionof a larger chip or directly wire-bonded to the package substrate.Because a wire bond connection has to be made to all of the chips in thestack, it is required that a chip in the stack be smaller than a chipunderneath it. As a result, the size of the chips that can be stacked islimited. To be able to stack chips of the same size, a spacer ofspecific height and dimension can be inserted between the chips. Wu, L.,Wang, Y. P., Hsiao C. S., “Innovative Stack-Die Package—S2BGA,” 52^(nd)Electronic Components and Technology Conference, May 2002, San Diego,Calif. Such spacer will separate the chips and will allow enough workingdistance to enable a wire bond connection. However, the addition of aspacer increases the height of the stack and also adds extra processsteps that may complicate and deteriorate the assembly and reliabilityof the stack. Further, when a spacer is used, it is difficult to make anelectrical connection between chips in the stack.

To overcome the limitations of wire bond IC stacks, an alternateapproach involving use of conductive thru-vias fabricated within the IChas also been introduced, by Sunohara, M., Fujii, T., Hoshino, M.,Yonemura H., Tomisaka, M., Takahashi, K., “Development of Wafer Thinningand Double-Sided Bumping Technologies for the Three-dimensional StackedLSI,” 52^(nd) Electronic Components and Technology Conference, May 2002,San Diego, Calif. In this approach, vias are fabricated into the IC andfilled with a conductor. During subsequent process steps, electricalconnections are made to these thru-vias, the IC wafer is attached to acarrier wafer, thinned down to expose the thru-via conductor, insulatedon the backside and attached to another IC formed using similar processflow. A significant number of expensive process steps are applied to anactive, and often thin, IC wafer in this approach. Expensive IC area isused to fabricate conductive thru-vias. In addition, the resultantstructure may have poor thermo-mechanical reliability because of a largedifference in the Coefficient of Thermal Expansion (CTE) between siliconand the conductive material that is used to fill a thru-via. Assemblyprocesses during IC stacking may introduce mechanical stress that canlead to silicon fracture.

It would be desirable to have a structure and a corresponding processflow that can be easily integrated with semiconductor back end of theline (BEOL) processes and as a result, provides an effective way toeither stack ICs on top of each other or assemble them verticallyadjacent to each other achieving, in the end, a higher level of systemintegration by utilising three dimensions.

SUMMARY OF THE INVENTION

It is therefore an aspect of the present invention to provide asemiconductor with pins that facilitate electrical connection.

It is another aspect of the invention to provide a method ofmanufacturing such semiconductor dies.

It is still another aspect of the invention to provide a plurality ofstructures that can be constructed using such semiconductor dies.

The invention is directed to methods of fabricating semiconductor diewith micro-pins and several embodiments of the structure. The micro-pinsfabricated on the semiconductor die can be utilised to stack ICs on topof each other or vertically, or horizontally adjacent to each other. Themicro-pins can be used to establish temporary chip attachment points fortesting purposes. The micro-pins can also be used to assembleheterogeneous systems; for example, involving attachment of a photodiode on a silicon chip.

Thus, one aspect of the invention is directed to a semiconductor diecomprising a planar semiconductor member; and a plurality of conductivepins extending from the semiconductor member in a direction parallel toa plane of the semiconductor member. The pins may extend directly fromthe semiconductor member. The semiconductor die may have a plurality ofsides, with the pins extending from at least one of the sides or all ofthe sides, generally in a direction perpendicular to a plane of thesemiconductor member.

The semiconductor die may be combined with at least one additionalsemiconductor die, the semiconductor dies being disposed one overanother so that respective pins of the semiconductor die are stacked oneover to facilitate electrical contact with one another. The respectivepins may be diffusion bonded to one another to provide the electricalcontact or an electrically conductive material may be disposed betweenthe respective pins so as to provide the electrical contact. Thecombination may further comprise a substrate on which the combination ismounted. The substrate may be formed of a semiconductor material. Asecond substrate, on which the first substrate may be mounted, may beformed of an insulating material.

The semiconductor die in accordance with the invention may be combinedwith at least one other semiconductor die so that successive ones of thesemiconductor dies are assembled with at least one wiring substratebetween dies, so as to form a solid rectangle or cube. The at least onewiring substrate may provide electrical connections between the dies.

At least one additional semiconductor die may be assembled to theoutside of the solid rectangle, the additional semiconductor die havingelectrical connections to at least one of the dies in the solidrectangle. The wiring substrates may have opening therein to facilitatemanagement of heat.

The invention is also directed to a semiconductor die comprising aplanar semiconductor member; with a plurality of first electricallyconductive pins formed on a surface of the semiconductor member, thepins having portions extending along a side of the semiconductor member.This semiconductor member may be combined with a second semiconductormember having second electrically conductive pins formed on a surface ofthe second semiconductor member, the second pins having portionsextending along a side of the second semiconductor member, at least aportion of the first pins and the second pins being disposed on thesemiconductor members so as to align with one another when thesemiconductor members are placed in close proximity to one another, sothat electrical contact between respective ones of the first pins andthe second pins is facilitated. This combination may further comprise atleast one additional semiconductor member, the additional semiconductormember having additional pins, the additional pins having portionsextending along a side of the additional semiconductor member, theadditional pins being disposed on the additional semiconductor member soas to align with additional pins on an additional side of the firstsemiconductor member or the second semiconductor member when theadditional semiconductor member is placed in close proximity to thefirst semiconductor member or the second semiconductor, so thatelectrical contact between respective ones of the additional pins andthe first pins or second pins is facilitated. The semiconductor membersare disposed so as to be coplanar.

The invention is further directed to a semiconductor die substratecomprising a planar semiconductor member, the member having a pluralityof micro-cups formed on a surface thereof, at least a portion of themicro-cups being sized, shaped and positioned so as to receivemicro-pins. The semiconductor die may be combined with a secondsemiconductor die. The second semiconductor die may comprise a planarsemiconductor member; a plurality of conductive micro-pins extendingfrom the semiconductor member in a direction parallel to a plane of thesemiconductor member, with the micro-pins being received in themicro-cups. Preferably, the semiconductor die substrate and the secondsemiconductor die are perpendicular to one another. The combination mayfurther comprise at least one bracket member, the bracket member havinga first surface in contact with the semiconductor die substrate and asecond surface in contact with the second semiconductor die.

The combination may also further comprise an adhesive material disposedbetween the semiconductor members to facilitate the semiconductormembers being secured to one another.

The invention is also directed to a method for forming a semiconductordie, comprising forming a trench in a surface of the die; filing thetrench with a sacrificial material; patterning the die to form a seriesof channels extending substantially perpendicularly to the trench;depositing a conductive material in the channels; removing at least aportion of the sacrificial material; and removing portions of the dieunder the trench so as to separate a portion of the die on one side ofthe trench from a portion on another side of the trench. The method mayfurther comprise patterning the sacrificial material so that thechannels extend so as to be partially in a portion of the die andpartially a portion of the sacrificial material. The sacrificialmaterial may be patterned to a depth greater than the die. The removingmay be performed by grinding or etching of the die.

The die may be part of a wafer having a plurality of dies, and thetrench may be a dicing lane of the wafer. The sacrificial material maybe a polymer or a photoresist. The conductive material may be one of ametal, a conductive paste, and a solder.

The method may further comprise depositing an adhesion layer in thechannels prior to depositing the conductive material. The adhesion layermay be formed of a polymer or a silicon oxide.

The invention is further directed to a method for forming asemiconductor die, comprising forming a trench in a surface of the die;filing the trench with a sacrificial material; patterning the die toform a series of channels extending substantially perpendicularly to thetrench; depositing a conductive material in the channels; removingportions of the die under the trench; and removing at least a portion ofthe sacrificial material so as to separate a portion of the die on oneside of the trench from a portion on another side of the trench.

In accordance with one additional aspect, the invention is also directedto a method of forming substrates with at least one micro-cup,comprising forming at least one via in the substrate; coating the atleast one via with a conductive material or a conductive and adhesivematerial to form the micro-cup; and coating adhesive material on thesubstrate to facilitate attachment of a device having at least one pin,the at least one pin being sized, shaped and positioned to be receivedin a respective one of the at least one via. The method may furthercomprise assembling the device to the substrate.

BRIEF DESCRIPTION OF THE DRAWINGS

These and other aspects, features, and advantages of the presentinvention will become apparent upon further consideration of thefollowing detailed description of the invention when read in conjunctionwith the drawing figures, in which:

FIG. 1 is a plan view of an embodiment of a semiconductor die withmicro-pins of the present invention.

FIGS. 2A-2Q are cross sectional side views showing process steps tofabricate a semiconductor die with micro-pins as well as the forming ofelectrical connection between micro-pins and devices on thesemiconductor die, while FIG. 2B(i) is a plan view of a portion of FIG.2A.

FIGS. 3A-3F are side views of an alternate embodiment showing stackingof semiconductor chips using micro-pins in accordance with the presentinvention.

FIGS. 4A-4C are side views of an alternate embodiment showing attachmentof semiconductor die stack on another semiconductor die, interposer, ora substrate.

FIGS. 5A-5B are side views of an alternate embodiment of the inventionshowing attachment of semiconductor die stack on a substrate.

FIGS. 6A-6B are frontal and edge view of a semiconductor die withmicro-pins.

FIG. 7A-7B are side views of an alternate embodiment showingsemiconductor chips with micro-pins assembled vertically adjacent toeach other on a substrate.

FIG. 8A-8B is an alternate embodiment showing semiconductor chips withmicro-pins assembled in a cube surrounding by multiple substrates.

FIG. 9 is a side elevational view of semiconductor chip cube of FIG. 8A.

FIG. 10A-10D are sectional views showing process steps to fabricatemicro-cups on a substrate.

FIG. 11A is a plan view and FIG. 11B is a cross sectional view whichillustrate an alternate embodiment showing vertical or horizontalattachment of devices, such as Group III-V devices, on a silicon chipusing micro-pins and micro-cups.

FIG. 12 is a plan view of horizontal tiling of semiconductor dies inaccordance with yet another aspect of the invention.

DESCRIPTION OF THE INVENTION

Variations described for the present invention can be realized in anycombination desirable for each particular application. Thus particularlimitations, and/or embodiment enhancements described herein, which mayhave particular advantages to the particular application need not beused for all applications. Also, it should be realized that not alllimitations need be implemented in methods, systems and/or apparatusincluding one or more concepts of the present invention.

Referring to the drawings more particularly by reference numbers, FIG. 1shows an embodiment of a semiconductor die 20 with micro-pins 22 of thepresent invention. The semiconductor die may include plurality ofmicro-pins on any one or all sides of the die. These micro-pins areelectrically connected to devices on the die 20. Typical dimensions forthe micro-pins 22 may be a length of 1 to 1000 microns, a width of 1 to500 microns and a depth of 1 to 800 microns in the direction into thedie 20, although these dimensions are provided merely by way of example.Actual dimensions will depend on the requirements of the specificapplication.

FIG. 2A and FIG. 2B show first steps in the process of fabricatingsemiconductor die with micro-pins 22. A portion 24 of a typicalsemiconductor wafer having chips 20 separated by dicing lanes or kerfs26, extending in two mutually perpendicular directions so as to fromrectangular dies, is shown in FIG. 2A. The widths of these dicing lanesor kerfs 26 is application dependent.

As shown in FIG. 2B and FIG. 2B(i), trenches 28 may be created on thewafer with known wet or dry etching processes. The trenches 28, havingdimensions which may vary with the application, may be placed at leastpartially in the dicing lanes or kerfs 26, and have extensions 30 whichare used to form the micro-pins 22. The trenches 28 and their extensions30 may be filled with a sacrificial epoxy, polymer, photoresist orsimilar material 31 as shown in FIG. 2C.

Using known photolithographic process, the polymer or polymer likematerial may be patterned and etched using wet or dry etching processesas shown in FIGS. 2D(i) and 2D(ii). The wet or dry etching processes maybe selective with respect to semiconductor material and may allow theformation of a specific structure, such as, for example, the channel 32of FIG. 2D(i) or the step structure 34 as shown in FIG. 2D(ii).

The patterned and etched features may be filled with conductive materialsuch as copper, metallic paste, solder, etc. to form micro-pins 22 asshown in FIG. 2E(i), for the case of the pattern formed in FIG. 2D(i),and the micro-pins 22A of FIG. 2E(ii), for the case of the patternformed in FIG. 2D(ii). Prior to filling the patterned features withconductive material, layers of passivation films such as silicon oxideor silicon nitride, adhesive films such as polymeric or epoxy materialsor metals such as indium, tin, and plating seed or barrier layers suchas titanium, tantalum, chromium or copper may be deposited in thepatterned features.

As an optional step, additional conductive materials 36 such as metalsor conductive polymers may be patterned, coated or deposited on top ofmicro-pins as shown in FIG. 2F(i) and FIG. 2F(ii). The polymer likematerial 31 deposited in the trenches as described above with respect toFIG. 2C may be removed partially or completely from the trenches asshown in FIG. 2G(i) and FIG. 2G(ii).

Using a laser saw or dicing saw or any other known method, thesemiconductor wafer may be diced from the back side as shown in FIG.2H(i) and FIG. 2H(ii). Waste portions 40 are discarded. As part of thedicing/singulating process, the wafer may temporarily be attached to adicing tape or substrate (not shown). The process sequence described inFIG. 2 a-2 h results into individual semiconductor dies with micro-pins22 or 22A. Micro-pins 22 are essentially embedded in the surface of die20. Micro-pins 22 then extend in a cantilevered fashion horizontallyaway from die 20. Micro-pins 22A also may be embedded in the surface ofdie 20. However, micro-pins 22A have a portion 23 extending downward andagainst the vertical side surface of die 20.

An alternate process of fabricating semiconductor die with micro-pins isdescribed in FIGS. 21-2K. Preferably, immediately following process stepdescribed in FIG. 2F(i) or FIG. 2F(ii), the wafer may be ground from thebackside as shown in FIG. 2I(i) and FIG. 2I(ii). During the backsidegrind step, the front side of the semiconductor wafer temporarily may beattached to an adhesive tape or a substrate (not shown). The backsidegrind step may include a coarse grind, a fine grind and a chemicalmechanical polishing (CMP) steps. The backside grinding of thesemiconductor wafer may stop when the polymer like film or conductivematerial is exposed as shown in FIG. 2I(i) and FIG. 2I(ii).

The semiconductor material on the backside of the wafer may be removedor etched using wet or dry processes as shown in FIG. 2J(i) or FIG.2J(ii). The polymer like material deposited in the trenches as describedabove with respect to FIG. 2C may be removed as shown in FIG. 2K(i) andFIG. 2K(ii). The process sequence described in FIG. 21-2K results inindividual semiconductor dies with micro-pins 22B or 22C, which extendbelow the back side of the respective dies 20. Referring to FIG. 2K(i)specifically, micro-pins 22B are formed with a lower portion 25 thatextends below die 20. Referring to FIG. 2K(ii) specifically, micro-pins22C extend downward and against the vertical side surface of die 20 andbelow die 20. Micro-pins 22B and 22C are especially advantageous inallowing dies having micro-pins with these configuration to be stacked,as described in more detail below.

The semiconductor dies with micro-pins produced using the process ofFIG. 2I to FIG. 2 k can be very thin (1 to 400 micrometers thick) andthe requirement of dicing the wafer to obtain individual dies isavoided. Although not specifically mentioned above, the step involvingremoval of polymer like material, as described with respect to FIG. 2K,may be exercised prior to the step of grinding the wafer from the backas described with respect to FIG. 21.

FIG. 2L FIG. 2Q illustrate steps in forming an electrical connectionbetween the micro-pins and devices on the semiconductor die. A sectionalview of a semiconductor die on a semiconductor wafer at the end of finalpassivation step, having a final passivation layer 42 is shown in FIG.2L. At this point, die terminal pads 44 are covered with the finalpassivation layer 42. Micro-pin fabrication process steps described inFIG. 2B to FIG. 2C may be applied to the semiconductor wafer 20 as shownin FIG. 2M, to produce, for example, micro-pins 22A.

Using known photolithographic process, a photo-polymeric material 31 maybe patterned onto the wafer in FIG. 2N. As part of process stepillustrated in FIG. 2D, the photo-polymer material 31 may be patternedsuch that it uncovers the trench and die terminal pads 44 which arecovered in FIG. 2N. The polymer like material 31 in the trench and thepassivation material 42 on top of die terminal pads 44 may be partiallyetched (partially uncovering a terminal pad 44A) or completely etched(completely uncovering a terminal pad 44B) using wet or dry processes asshown in FIG. 20, in the manner described with respect to FIG. 2D(i) andFIG. 2D(ii).

Referring to FIG. 2P, the patterned and etched features may be filledwith conductive material 48 such as copper, metallic paste, solder, etcto form micro-pins 22C. Prior to filling the patterned features withconductive material, layers of passivation films such as silicon oxideor silicon nitride, adhesive films such as polymeric or epoxy materialsor metals such as indium, tin, and plating seed or barrier layers suchas titanium, tantalum, chromium and copper may be deposited in thepatterned features.

Referring to FIG. 2Q, the photo-polymer material 46 may be removed fromthe wafer surface to produce the structure shown therein. The processsteps described with respect to FIG. 2L to FIG. 2Q may be performed.Electrical connections 50A and 50B may then be made to the micro-pins22A and to devices (not shown) on the die 20 by means of die terminalpads 44A and 44B. The wafer may be subjected to process steps describedwith respect to FIG. 2F to FIG. 2 h or FIG. 2I to FIG. 2K to obtain asemiconductor die with micro-pins.

FIG. 3A to FIG. 3F are side views of various embodiments showingstacking of semiconductor chips using micro-pins and/or joining materialformed on top of micro-pins. In FIG. 3A the dies 20 have micro-pins 22B.In FIG. 3B the dies 20 have micro-pins 22A, which extend below the lowersurface or back side of dies 20. The application of suitable heat andpressure may result in diffusion bonding of the micro-pins. Theembodiment of FIG. 3C is similar to that of FIG. 3A, but a joiningmaterial 54 is used between the micro-pins 22B of successive dies 20. InFIG. 3D, a joining material 54 is used between the micro-pins 22C ofsuccessive dies 20. In FIG. 3E, a chip formed on a relatively smallerdie 20A of is stacked on top of a chip formed on a relatively larger die20B. A joining material 54 is used between the bottom surface ofmicro-pins 22B and the top surface of die 20B. In FIG. 3F, the lowersurfaces of micro-pins 22C of a die 20A may be placed on the uppersurface of a die 20B, with or without the use of a joining layer. If nojoining layer is used, diffusion bonding may be utilised. Theseembodiments may be employed when stacking of thin semiconductor chips ofsame or different sizes on top of each other is desired to gainelectrical performance or to achieve a compact, dense system that fullyutilises three-dimensional integration.

FIG. 4A to FIG. 4C are side elevational views of alternate embodimentsshowing attachment of a semiconductor dies stack 60 on anothersemiconductor 8 die, on an interposer, or on a substrate. As shown inFIG. 4A, the semiconductor die stack 60, comprising memory chips, forexample, may be attached to a semiconductor die, a substrate or aninterposer 61 to construct a complex, high performance multi-chip moduleshown generally as 62. Substrate 61 may itself have micro-pins of thetype 22A to which stack 60 is attached. Attachment may be effected usingattachment members 63 such as a solder ball, conductive adhesive, or ametal, as is well known in the art. Attachment members 63A may be usedto affix and electrically connect multi-chip module 62 to the next levelof packaging.

FIG. 4B is a side elevational view of stacking of the chip module 62 ofFIG. 4A onto another semiconductor interposer 68. Similarly, as shown inFIG. 4C, chip modules 62 of kind illustrated in FIG. 4A may be stackedon top of each other, by interposing a spacer 70 to achieve an extremelydense high performance system, shown generally as 72.

FIG. 5A and FIG. 5B are side elevational views of alternate embodimentsshowing attachment of a semiconductor die stack 60 to anon-semiconductor substrate 80 of a next level of packaging such as aceramic substrate, FR-4 board or a high density substrate. In FIG. 5A,the stack 60 of dies is connected directly to the non-semiconductorsubstrate 80 by means of a metal, solder or conductive adhesive, whichmay be in the form of attachment members 82. An underfill material 83,such as an epoxy or polymer resin may then be applied. In FIG. 5B, achip module shown generally as 65 is connected directly to a substrate84 by means of a metal, solder conductive adhesive, which may be in theform of attachment members 86. Substrate 84 is then connected to asubstrate 80 by means of a metal, solder, or conductive adhesive, whichmay be in the form of attachment members 88. An underfill 83 may also beapplied. These embodiments may be used in creating a high performancecomputer where the substrates shown in FIG. 5A or FIG. 5B are thenconnected in parallel, through a backplane (not shown), to a cabinetpanel (also not shown).

FIG. 6A and FIG. 6B are plan and perspective views, respectively, of asemiconductor die 20 with micro-pins 22 on one of its sides.

FIG. 7A and FIG. 7B are perspective views of an alternate embodimentshowing semiconductor chips or dies 20 with micro-pins 22 assembledvertically adjacent to each other on a substrate. The semiconductordies, each with micro-pins on one of its sides, may be attached to asubstrate vertically adjacent to each other as shown in FIG. 7A. Thisembodiment is useful when it is desired to achieve a high packingdensity or to provide a highly compact system, by assembling chipsadjacent to each other rather, than on top of each other. Assemblingchips adjacent to each other is especially attractive when the chipshave differing dimensions. In contrast to attaching a die so that it isflat on the substrate, vertical attachment of semiconductor dies usingmicro-pins as described by this embodiment also assists in reducingthermo-mechanical stresses arising as a result of difference in theCoefficient of Thermal Expansion (CTE) that typically exists between asemiconductor die and a non-semiconductor substrate such as an FR-4board or a high density substrate. This is because the distance from dieneutral point (DNP) on the substrate is significantly reduced invertical assembly, as opposed to that in horizontal assembly. Verticallyassembled chips as shown in FIG. 7A may be firmly supported by speciallydesigned mechanical clamps or fixtures 92 as shown in FIG. 7B.

FIG. 8A is an alternate embodiment showing semiconductor chips or dies20 with micro-pins 22 assembled in a rectangular solid or a cube andattached to wiring backplanes, substrates or interposers 96, and in theform of a cube 100. This is a useful embodiment when an extremely densesystem is desired. For example, memory chips can be assembled in a cubesurrounding by wiring planes and respective processor or logic chips 102can be assembled on the wiring substrate as shown in FIG. 8B. As such,processor or logic chips can readily access memory that is assembled inthe cube. The semiconductor chips or dies 29 with micro-pins 22 can beassembled to form a rectangular solid or more particularly the cube 100by joining the chips to the wiring backplanes, substrates or interposers96 having dual or single sided wiring and a surface metallurgy that isable to bond by means of metal, solder or electrically conductiveadhesive. In this case, the wiring backplanes or substrates will formthe faces of the cube 100 with singular or multiple chips inside suchcube. Once such system is constructed, the additional chips 102 can bereadily attached to the outer side of the wiring backplanes orsubstrates forming the cube by similar means of metal, solder orelectrically conductive adhesive.

FIG. 9 shows a side elevational view of the cube system shown in FIG. 8.The wiring plane or substrates 96 of the cube system may haveholes/slots 104 in them to allow for thermal management, as for example,by circulating a cooling fluid through the holes or slots 104. Thewiring planes 96A at opposite sides of the cube 100 may additionallyhave connectors 106 that allow attachment of the system to the nexthigher level of packaging.

FIG. 10A to FIG. 10D are sectional views showing process steps tofabricate micro-cups on a substrate that may be useful in makingelectrical and mechanical connection between semiconductor dies withmicro-pins and the substrate, as well as to other components on thesubstrate. Via cups 108 may be formed, by any known wet or dry chemicalprocess, in the substrate 110 as shown in FIG. 10A. The substrate may bea semiconductor die, package interposer, or of other forms as used inthe electronics industry. Vias for this purpose may also vary in sizeand shape. The vias may be filled or coated with adhesive and/orconductive material 112 as shown in FIG. 10B. Such adhesive orconductive material may help in achieving an electrical and mechanicalconnection between the device with micro-pins and the substrate.Micro-pins may be connected to other points on the substrate by use ofelectrical connections that are made to micro-cups, by for example, athin electrically conductive layer 114, deposited on the surface ofsubstrate 110, which extends into cups 108, as shown in FIG. 10C(i) andFIG. 10C(ii). Additionally, a layer of adhesive material 116 may becoated on the substrate to act as “glue” between the semiconductor diewith micro-pins and the substrate 110. Layer 116 may be one of apolymer, an epoxy, or a silicon dioxide layer which forms a bond undersuitable temperature and pressure conditions. A device 118 havingmicro-pins 122 is assembled to a substrate 110, as shown in FIG. 10D.

FIG. 11A and FIG. 11B illustrate an alternate embodiment showingvertical or horizontal attachment of devices, such as a Group III-V(compound semiconductor, such as GaAs, InP) device or other device 124,on a silicon chip or die 140. The die 140 has micro-pins 142, while thedevice 124 has micro-pins 144, which are received in micro-cups 148.This embodiment is useful when it is necessary to build heterogeneoussystem. The device 124 is attached at a point in the fabrication processlater than that at which micro-pins 143 are formed.

FIG. 12 illustrates an embodiment of the invention wherein dies 20having micro-pins 22 are arranged in a horizontal plane so that the endsof micro-pins of one die are in physical contact with the ends ofmicro-pins 22 of an adjacent die. Although the ends are shown as beingin contact, in principle, the dies may be positioned so that the sidesof the micro-pins 22 of one die contact the sides of the micro-pins 22of an adjacent die. In either case, electrical connection between themicro-pins 22 may be made with a solder, a conductive adhesive, or bydiffusion bonding of the micro-pins of one die to the micro-pins of anadjacent die under suitable temperature and pressure conditions.

This “tiling” arrangement is especially advantageous in that it providesan extremely high bandwidth connection between the dies.

The present invention advantageously has advantages and other uses notspecifically discussed above. For example, micro-pins and micro-cups mayprovide attachment or connection points for the testing of chips. Insuch case, micro-pins can temporarily be used to test the chips whenfabricated, as well as attachment of chips to next level of packaging,after testing.

While certain exemplary embodiments have been described and shown in theaccompanying drawings, it is to be understood that such embodiments aremerely illustrative of and not restrictive on the broad invention, andthat this invention not be limited to the specific constructions andarrangements shown and described, since various other modifications mayoccur to those ordinarily skilled in the art.

It is noted that the foregoing has outlined some of the more pertinentobjects and embodiments of the present invention. The concepts of thisinvention may be used for many applications. Thus, although thedescription is made for particular arrangements and methods, the intentand concept of the invention is suitable and applicable to otherarrangements and applications. It will be clear to those skilled in theart that other modifications to the disclosed embodiments can beeffected without departing from the spirit and scope of the invention.The described embodiments ought to be construed to be merelyillustrative of some of the more prominent features and applications ofthe invention. Other beneficial results can be realized by applying thedisclosed invention in a different manner or modifying the invention inways known to those familiar with the art. Thus, it should be understoodthat the embodiments has been provided as an example and not as alimitation. The scope of the invention is defined by the appendedclaims.

1. A semiconductor die comprising: a planar semiconductor member; and aplurality of conductive pins extending from said semiconductor member ina direction parallel to a plane of said semiconductor member.
 2. Thesemiconductor die of claim 1, wherein said pins extend directly fromsaid semiconductor member.
 3. The semiconductor die of claim 1, whereinsaid semiconductor has a plurality of sides, and wherein said pinsextend from at least one of said sides.
 4. The semiconductor die ofclaim 1, wherein said semiconductor has a plurality of sides, andwherein said pins extend from all of said sides.
 5. The semiconductordie of claim 1, wherein said pins are micro-pins having a of length of 1to 1000 microns, a width of 1 to 500 microns and a depth of 1 to 800microns in the direction into the die.
 6. The semiconductor die of claim1, wherein said semiconductor has a plurality of sides, and wherein saidpins extend along said sides in a direction perpendicular to a plane ofsaid semiconductor member.
 7. The semiconductor die of claim 6, incombination with at least one additional semiconductor die, saidsemiconductor dies being disposed one over another so that respectivepins of said semiconductor die are stacked one over another tofacilitate electrical contact with one another.
 8. The combination ofclaim 7, wherein said respective pins are diffusion bonded to oneanother to provide said electrical contact.
 9. The combination of claim7, further comprising an electrically conductive material disposedbetween said respective pins so as to provide said electrical contact.10. The combination of claim 7, further comprising a substrate on whichsaid combination is mounted.
 11. The combination of claim 10, whereinsaid substrate is formed of a semiconductor material.
 12. Thecombination of claim 10, further comprising a second substrate, saidsecond substrate being formed of an insulating material.
 13. Thesemiconductor die of claim 1, in combination with at least one othersemiconductor die of claim 1, successive ones of said semiconductor diesbeing assembled with at least one wiring substrate between dies, said atleast one wiring substrate providing electrical connections between saiddies.
 14. The combination of claim 13, wherein said dies and said atleast one substrate are assembled so as to form a solid rectangle. 15.The combination of claim 14, further comprising at least one additionalsemiconductor die assembled to the outside of said solid rectangle, saidadditional semiconductor die having electrical connections to at leastone of said dies in said solid rectangle.
 16. The combination of claim13, wherein said wiring substrates have openings therein to facilitatemanagement of heat.
 17. A semiconductor die comprising: a planarsemiconductor member; and a plurality of first electrically conductivepins formed on a surface of said semiconductor member, said pins havingportions extending along a side of said semiconductor member.
 18. Thesemiconductor member of claim 17, in combination with: a secondsemiconductor member having second electrically conductive pins formedon a surface of said second semiconductor member, said second pinshaving portions extending along a side of said second semiconductormember, at least a portion of said first pins and said second pins beingdisposed on said semiconductor members so as to align with one anotherwhen said semiconductor members are placed in close proximity to oneanother, so that electrical contact between respective ones of saidfirst pins and said second pins is facilitated.
 19. The combination ofclaim 18, further comprising at least one additional semiconductormember, said additional semiconductor member having additional pins,said additional pins having portions extending along a side of saidadditional semiconductor member, said additional pins being disposed onsaid additional semiconductor member so as to align with additional pinson an additional side of said first semiconductor member or said secondsemiconductor member when said additional semiconductor member is placedin close proximity to said first semiconductor member or said secondsemiconductor, so that electrical contact between respective ones ofsaid additional pins and said first pins or second pins is facilitated.20. The combination of claim 19, wherein said semiconductor members aredisposed so as to be coplanar.
 21. A semiconductor die substratecomprising: a planar semiconductor member, said member having aplurality of micro-cups formed on a surface thereof, at least a portionof said micro-cups being sized, shaped and positioned so as to receivemicro-pins.
 22. The semiconductor die of claim 21, in combination with:a second semiconductor die, said second semiconductor die comprising: aplanar semiconductor member; a plurality of conductive micro-pinsextending from said semiconductor member in a direction parallel to aplane of said semiconductor member, said micro-pins being received insaid micro-cups.
 23. The combination of claim 22, wherein saidsemiconductor die substrate and said second semiconductor die areperpendicular to one another.
 24. The combination of claim 22, furthercomprising at least one bracket member, said bracket member having afirst surface in contact with said semiconductor die substrate and asecond surface in contact with said second semiconductor die.
 25. Thecombination of claim 22, further comprising an adhesive materialdisposed between said semiconductor members to facilitate saidsemiconductor members being secured to one another. 26.-38. (canceled)